LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

--input comes from the PC and PC+4 from the adder
entity regdecode is
  port ( 
    CLK							     :		 in	std_logic;
    nReset         :   in std_logic;
    iden           :   in std_logic;
    dPC4           :   in std_logic_vector (31 downto 0);     --in from fetch
    dREG_RDAT1     :   in std_logic_vector (31 downto 0);     --in from fetch PC+4 addr
    dREG_RDAT2     :   in std_logic_vector (31 downto 0);     --in from fetch PC+4 addr
    dRt            :   in std_logic_vector (4 downto 0); --instruction(20 downto 16)
    dRd            :   in std_logic_vector (4 downto 0); --instruction(15 downto 11)
    dRs            :   in std_logic_vector (4 downto 0);
    dImmExtend        :   in std_logic_vector (31 downto 0);
    dWBctrl        :   in std_logic_vector (3 downto 0);
    dMEMctrl       :   in std_logic_vector (2 downto 0);
    dEXctrl        :   in std_logic_vector (6 downto 0);
    dhalt          :  in std_logic;

    exPC4          :   out std_logic_vector (31 downto 0);    --out to decode
    exREG_RDAT1    :   out std_logic_vector (31 downto 0);     --out to decode
    exREG_RDAT2    :   out std_logic_vector (31 downto 0);     --out to decode
    exRt           :   out std_logic_vector (4 downto 0); --instruction(20 downto 16)
    exRd           :   out std_logic_vector (4 downto 0); --instruction(15 downto 11)
    exRs           :   out std_logic_vector (4 downto 0);
    exImmExtend       :   out std_logic_vector (31 downto 0);
    exWBctrl       :   out std_logic_vector (3 downto 0);
    exMEMctrl      :   out std_logic_vector (2 downto 0);
    EXctrl         :   out std_logic_vector (6 downto 0);
    exhalt         : out std_logic
  );
end regdecode;

architecture arch of regdecode is
  signal q0, n0  : std_logic_vector (31 downto 0);  --PC4
  signal q1, n1  : std_logic_vector (31 downto 0);  --REG_RDAT1
  signal q2, n2  : std_logic_vector (31 downto 0);  --REG_RDAT2
  signal q3, n3  : std_logic_vector (4 downto 0);  --Rt (instruction(20-16)
  signal q4, n4  : std_logic_vector (4 downto 0);  --Rd
  signal q5, n5  : std_logic_vector (31 downto 0);  --Extend
  signal q6, n6  : std_logic_vector (3 downto 0); --WBctrl
  signal q7, n7  : std_logic_vector (2 downto 0); --MEMctrl
  signal q8, n8  : std_logic_vector (6 downto 0); --EXctrl
  signal q9, n9  : std_logic_vector (4 downto 0); --Rs
  signal q10, n10 : std_logic;
  
begin
  
  proc : process(CLK,nReset)
  begin
    if (nReset = '0')  then
      q0 <= x"00000000";
      q1 <= x"00000000";
      q2 <= x"00000000";
      q3 <= "00000";
      q4 <= "00000";
      q9 <= "00000"; -- Rs
      q5 <= x"00000000";
      q6 <= (others => '0');
      q7 <= (others => '0');
      q8 <= "0000000";
      q10 <= '0';

    elsif rising_edge(CLK) then
      q0 <= n0;
      q1 <= n1;
      q2 <= n2;
      q3 <= n3;
      q4 <= n4;
      q5 <= n5;
      q6 <= n6;
      q7 <= n7;
      q8 <= n8;
      q9 <= n9; 
      q10 <= n10;

    end if;
  end process proc;

  n0 <= dPC4 when iden = '1' else
        q0 when iden = '0' else
        x"00000000";
  n1 <= dREG_RDAT1 when iden = '1' else
        q1 when iden = '0' else
        x"00000000";
  n2 <= dREG_RDAT2 when iden = '1' else
        q2 when iden = '0' else
        x"00000000";
  n3 <= dRt when iden = '1' else
        q3 when iden = '0' else
        "00000";
  n9 <= dRs when iden = '1' else
        q9 when iden = '0' else
        "00000";
  n4 <= dRd when iden = '1' else
        q4 when iden = '0' else
        "00000";
  n5 <= dImmExtend when iden = '1' else
        q5 when iden = '0' else
        x"00000000";
  n6 <= dWBctrl when iden = '1' else
        q6 when iden = '0' else
        (others => '0');
  n7 <= dMEMctrl when iden = '1' else
        q7 when iden = '0' else
        (others => '0');
  n8 <= dEXctrl when iden = '1' else
        q8 when iden = '0' else
        "0000000";
        
  n10 <= dhalt when iden = '1' else
        q10 when iden = '0' else
        '0';  
  

  exPC4            <= q0;
  exREG_RDAT1      <= q1;
  exREG_RDAT2      <= q2;
  exRt             <= q3;
  exRd             <= q4;
  exImmExtend         <= q5;
  exWBctrl         <= q6;
  exMEMctrl        <= q7;
  EXctrl           <= q8;  
  exRs             <= q9;
  exhalt           <= q10; 
  
     
end arch;